1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device.
2. Description of the Background Art
In recent years, there has been examined a method for manufacturing a vertical type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using silicon carbide.
According to one method disclosed in Japanese Patent Laying-Open No. 2009-158788 (Patent Literature 1), a substrate made of a semiconductor having a first conductivity type is first prepared. Onto the substrate, a material gas and a dopant gas of the first conductivity type are introduced to epitaxially grow a buffer layer thereon by means of vapor phase reaction. Onto the buffer layer, a material gas and a dopant gas of the first conductivity type are introduced to epitaxially grow a drift layer thereon by means of vapor phase reaction. Into a surface of the drift layer, ions of an impurity of a second conductivity type are implanted to form a body region. Into the body region, ions of an impurity of the first conductivity type are implanted to form a source region.
Meanwhile, according to one method disclosed in Japanese Patent Laying-Open No. 2011-023757 (Patent Literature 2), a p type layer is deposited, and then the p type layer is subjected to selective ion implantation of an n type impurity using a mask, whereby the p type layer is adapted to have a portion serving as an n type region. In this way, the n type region is formed between p type well layers.
According to the method disclosed in Japanese Patent Laying-Open No. 2009-158788, a path for a current flowing in the drift layer in the MOSFET is narrowed by a depletion layer extending from the p type body region, in the same principle as that for a JFET (Junction Field Effect Transistor). This makes it difficult to sufficiently reduce the on-resistance of the MOSFET.
Meanwhile, according to the method disclosed in Japanese Patent Laying-Open No. 2011-023757, the portion having its conductivity type converted from p type to n type as a result of the ion implantation constitutes the front-side surface of the drift layer. This portion includes: an impurity (also referred to as “p type impurity”) for providing the silicon carbide with p type; and an impurity (also referred to as “n type impurity”) having a doping concentration higher than that of the p type impurity to provide the silicon carbide with n type. In this case, the p type impurity and n type impurity canceling each other do not contribute to providing the conductivity types, but increase a total impurity concentration in the silicon carbide. In other words, the impurity concentration in the silicon carbide becomes unnecessarily high, with the result that carriers flowing in the silicon carbide are more frequently scattered by the impurities. This makes it difficult to sufficiently reduce the on-resistance of the MOSFET.